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MAX7060
280MHz to 450MHz Programmable
ASK/FSK Transmitter
Table 14. FSK High-Frequency 1 (FHigh1) Register (Address: 0x0A)
BIT
7:0
NAME
fhi[7:0]
FUNCTION
8-bit lower byte of high-frequency divider for FSK
The 4 MSBs of FHigh0, fhi[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (fhi[11:0])
are the fractional part of the divider.
Table 15. ASK Center-Frequency 0 (FCenter0) Register (Address: 0x0B)
BIT
7:0
NAME
fce[15:8]
8-bit upper byte of frequency divider for ASK
FUNCTION
Table 16. ASK Center-Frequency 1 (FCenter1) Register (Address: 0x0C)
BIT
7:0
NAME
fce[7:0]
8-bit lower byte of frequency divider for ASK
FUNCTION
The 4 MSBs of FCenter0, fce[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (fce[11:0)
are the fractional part of the divider.
When fce[11:0] are all zeros and ASK mode is selected (mode bit = 0), the PLL works in the fixed-N mode, which
reduces current consumption and reference spurs. Set pllbw bit high (Conf0 register, bit 5). For all other combinations,
the PLL works in fractional-N mode.
Table 17. FSK Low-Frequency 0 (FLow0) Register (Address:0x0D)
BIT
7:0
NAME
flo[15:8]
FUNCTION
8-bit upper byte of low-frequency divider for FSK
Table 18. FSK Low-Frequency 1 (FLow1) Register (Address: 0x0E)
BIT
7:0
NAME
flo[7:0]
FUNCTION
8-bit lower byte of low-frequency divider for FSK
The 4 MSBs of FLow0, flo[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (flo[11:0])
are the fractional part of the divider.
Table 19. Maximum and Minimum Values fo r Frequency Divider
DECIMAL VALUE
12.0220
2.9536
fhi[15:0], fce[15:0], flo[15:0]
0xC05A
0x2F42
Table 20. Frequency-Load (FLoad) Register (Address: 0x0F)
24
BIT
0
NAME
hop
FUNCTION
Effectively changes the PLL frequency to the ones written in registers 0x09 to 0x0E. This is a self-reset bit
and is reset to zero after the operation is completed.
Maxim Integrated
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